Just got a nice Gateway quad-core PC to speed up FPGA designs, so time to install Debian Linux on it. Install went smoothly, until I tried to boot into Linux for the first time. Then I get error messages:
ata1: softreset failed (device not ready)
ata2: softreset failed (device not ready)
and Linux hangs.
After a lot of Google-ing and hacking (and hair-pulling), I finally found the problem: The Debian installer set the boot partition on the SATA drive to /dev/sdb3, and it really should have been /dev/sda3. Still get the "softreset failed" errors, but Linux boots and seems to operate normally.
Thinking about the problem: I used a USB DVD drive for the install, and then disconnected it before booting. I suspect the DVD was sda and the sata disk was sdb during the install, and the sata became sda when booting without the DVD drive.
Friday, November 6, 2009
Monday, August 10, 2009
915MHz signal with a 100MHz A/D
I've been using a Radiotronix DP-1205 RF transceiver that operates in the 915MHz unlicensed ISM band. The power level, operating frequency, FM deviation, etc., are set using the SPI serial interface. So I decided to see if my MHZ100Q A/D PCB could see the signal. I bypassed the antialiasing filter and associated buffer, and then coupled the transceiver signal to the input.
It Works! The signal is low amplitude (less than 10% of full scale), and there are a lot of spurs 20dB down or so, but the carrier is clearly visible. The 902 to 928 MHz band is being undersampled at 100 MHZ so it shows up at 2 to 28 MHz in the digitized signal (in full compliance with Nyquist's rules).
The A/D is only spec'ed to 550 MHz, so I wouldn't trust the signal and distortion levels, but it's definitely a usable signal.
More details on the MHZ100Q project site at Source Forge.
It Works! The signal is low amplitude (less than 10% of full scale), and there are a lot of spurs 20dB down or so, but the carrier is clearly visible. The 902 to 928 MHz band is being undersampled at 100 MHZ so it shows up at 2 to 28 MHz in the digitized signal (in full compliance with Nyquist's rules).
The A/D is only spec'ed to 550 MHz, so I wouldn't trust the signal and distortion levels, but it's definitely a usable signal.
More details on the MHZ100Q project site at Source Forge.
Labels:
A/D,
DP1205,
MHZ100Q,
Nyquist,
Radiotronix,
undersampling
Wednesday, April 15, 2009
MHZ100Q - on sourceforge
I can now digitize one signal at 100MHz using my A/D card, capture in the Digilent Xilinx FPGA board, and upload to a PC via the USB port. I'm using Octave to upload and display the data, making a sort of oscilloscope. So I decided it's time to create a sourceforge open-source project.
It's http://mhz100q.sourceforge.net . Code is all in Subversion. It's all there, but I still need to create some build instructions and other documentation.
It's http://mhz100q.sourceforge.net . Code is all in Subversion. It's all there, but I still need to create some build instructions and other documentation.
Monday, March 2, 2009
Cypress CY7C68013A (FX2) USB to FPGA
I just got the USB interface working under Linux for the Digilent Nexys and Nexys 2 FPGA boards. Started with some ideas from the blog at braiden.org , updated the FX2 firmware and added from VHDL test code. Details at www.sensicomm.com/main/projects/fpga/ieee_fpga.shtml#nexys_usb .
Saturday, February 14, 2009
Noise-blog
Created a separate blog for less-technical happenings. (Signals here, random noise there). It's at noise-blog.sensicomm.com. Alternate is joerothweiler.blogspot.com (most noise-related names on blogspot are already taken).
Tuesday, December 9, 2008
Quad 100 MHz A/D PCB

The paying customers are taken care of for a while, so it's time to update the blog. I want to test some DSP on the FPGA (filters, RF signal modulation/demodulation, etc)., so I need A/D and D/A capability. I could buy a board, but it's more fun to build my own. So I settled on a quad, 8-bit, 100MHz board that interfaces to the Xilinx or Digilent board via the 100-pin FX/2 connector. The block diagram shows one of the 4 channels. As a test, I'm capturing a signal and displaying it on the VGA output. The signal is looking reasonable. More details on my website:http://www.sensicomm.com/main/projects/fpga/quad_100mhz_a2d.shtml
Monday, July 21, 2008
FPGA frequency counter code.

An FPGA project that does something useful: implements a frequency counter using the Xilinx Spartan 3AN development board. Basically consists of two counters and the AX8 uC core. The first counter generates a 1 Hz timing signal from the on-board 50 MHz crystal oscillator, and the second counter counts the signal under test. The AX8 core runs a simple program that reads the count value and formats it for display on the LCD.
The attached image is counting the frequency of a VEX RC transmitter using a 75.97 MHz crystal. The measured count is 75.971459 MHz, which is within 0.002% of the expected value. The development board uses an xtal oscillator marked AGXO-751L 50.000 A. I found a datasheet at www.inysa.es indicating that A versions are 100ppm, or 0.01%, so the measured value is well inside the tolerances.
I'll be posting the code when I get it ready.
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