Sensicomm LLC - Signals, sensors, comms

STM32 STM32F4DISCOVERY arm eval board and Linux

2012-01-27T12:54:00.000-05:00

Picked up this eval board at the last Embedded Systems Conference, and finally starting to work with it. The chip is a 168MHz ARM Cortex M4 with 12-bit A/D and D/A's . The eval board includes an accelerometer, microphone, and separate audio D/A chip, among other things. Pricing is really interesting. Here are Digikey quantity-1 prices:
STM32F4DISCOVERY $19.50
STM32F407VGT6     $16.00
STM32F103C8T6    $ 5.71
(The F407 is the main ARM chip, and the F103 is a smaller ARM chip used as a programming interface). So the eval board is actually cheaper than the chips on it.

The F407 chip has a built-in program loader using either the serial port or the USB port. Both are supported by Linux tools, so I'm ignoring the F103-based programming port and using the F407's USB port.

Connections: I have USB cables from my Linux box to both the F103's mini-USB connector at the top and the F407's micro-USB connector at the bottom. The mini-usb is just used to supply power to the board, and isn't necessary if an external supply is used.

The programming tool is dfu-util, from dfu-util.gnumonks.org . I downloaded and built the latest version from the git repository. To test it, I used the miniblink example program from the libopencm3 package at www.libopencm3.org/wiki/Downloads . libopencm3 uses the summon-arm toolchain, so I downloaded and built that as well so the example would compile easily. (This also means I now have 5 different versions of GNU GCC for ARM on my system: summon-arm (linaro-based), 2 from CodeSourcery, one from openembedded, and a built-from-scratch GCC. One of these days I'll simplify that).

To program, I connect a jumper between the 3V and boot0 pins on connector P2. After hitting the black reset button, lsusb shows USB devices connected as:
Bus 001 Device 011: ID 0483:df11 SGS Thomson Microelectronics STM Device in DFU Mode
Bus 001 Device 012: ID 0483:3748 SGS Thomson Microelectronics ST-LINK/V2
To use it without being root, I also added the line:
SYSFS{idVendor}=="0483", SYSFS{idProduct}=="df11", MODE="666" GROUP="plugdev" SYMLINK+="usb/stm32_dfu"
to plugdev (in Debian, I just created a new file in the /etc/udev/rules.d directory with this single line in it. Locations may be slightly different in other Linux distributions).
With that done, the command:
dfu-util --device 0483:df11 --alt 0 \
        --dfuse-address 0x08000000 \
        --download /miniblink.bin
works. I removed the jumper and hit reset again, and a single LED blinks, as expected.

So that's "Hello, World" for the STM32F4DISCOVERY. Now I can start doing real work with it.

Desampling using a Cascaded Integrator Comb filter

2011-11-23T16:29:00.000-05:00

Been working with a BeagleBoard for the last few months. Can't say much about the project but the Beagle is a nice ARM Linux platform. Finishing up, so now I have more time to update the MHZ100Q sourceforge project page.
I've now added a page describing the ideas behind the Cascaded Integrator-Comb (CIC) filter, and why it makes such a nice desampling filter for a high-rate data acquisition system. Input is 100MHz at 8 bits, and the output is any integer submultiple down to about 1kHz. The hardware resources in the FPGA are low: a set of 64-bit adders and registers, along with a reasonable amount of control logic.
The first version of the page is general description and overview. I plan to put more details of the math behind the CIC. In researching math and html, I found asciimathml.js . It's an open source JavaScript package that lets one embed equations into a webpage's text using simple LaTeX-like strings. I've used it internally and it's really nice to use. Should be live on the mhz100q page in the near future.

Embedded systems Conference

2011-09-30T20:47:00.001-04:00

I was at the Embedded Systems Conference in Boston this week, and Vgo Communications www.vgocomm.com had their telepresence robot roaming around on the exhibits floor. It was pretty unobtrusive, just wandering around the booths along with the rest of us.
I don't have any connection with them, just think it's a cute device.

Acer Laptop and Linux

2011-05-17T13:35:00.001-04:00

My old Averatec laptop started producing read errors on the hard drive - not good! I didn't lose anything important thanks to backups. PATA drives seem to be pretty much unavailable these days, so I ended up getting a new Acer 5253-BZ602 laptop. The first part of the fun with any new laptop is getting Linux installed and getting the peripherals working. Had to go with the latest Debian unstable distribution in order to get a working LAN driver. Most of the pieces are working now (graphics, wireless, ethernet, camera, etc). A web page with current status and driver info is at
http://www.sensicomm.com/main/linux/acer_5253/index.shtml .

USB inside an FPGA

2011-03-11T08:11:00.003-05:00

I'm working on updating the MHZ100Q project, and for a low-cost USB interface I want to put all of the USB functions inside the FPGA. So externally the interface consists of a connector and 3 resistors - can't get much lower cost than that.
I found 3 open source USB implementations:
1) opencores.org has the usb1_funct and usb_phy Verilog projects, which implement a USB device controller and physical layer (transceiver) respectively.
2) Joris has implemented the USB Communication Device Controller (CDC) protocol in VHDL. CDC devices basically look like an RS232 serial port to the host PC. This one is intended for use with an external PHY chip, and supports both full-speed(12MB/s) and high-speed(480MB/s) operation. Source is available on his website at www.xs4all.nl/~rjoris/fpga/usb.html .
3) Robert E. Jenkins of Johns Hopkins has published the USBF_IFC VHDL core, which includes both controller and PHY functions. It's set up for a XESS board, and is available at www.xess.com/projects/FPGA-USB-V2/readmeusb-v2.php .

Evaluation

I ported all 3 to my custom PCB, and did a brief evaluation.
1) The opencores modules went together easily, and Linux sees the USB device. I didn't implement any data transfers to/from the USB device, but it looks easy to do.
2) I decided to use the Joris controller with the opencores soft PHY instead of an external chip. That limits me to full speed, but saves parts. After a bit of hacking around to get the signals and polarities right, the combination worked great. (Mixing VHDL and Verilog wasn't a problem). His test program gave about 10 megabytes/second transfer rates, which is just about the maximum possible rate for a full-speed device. I've posted my files to demo this combination on my website at www.sensicomm.com/main/downloads/index.shtml (the specific file is 110310cdc_usb.tgz).
3) USBF_IFC took a bit of hacking to get it to run on my board. As stated on the project web page, it was a project for lab classes and still has some quirks.

I've been using USBF_IFC for several months now to test my hardware, but going forward I'm planning to use the Joris core. It's operation seems solid, being able to treat it as a serial device is nice for writing host software, and I can go to high speed if I add an external PHY in the future.

ATLYS HDMI

2011-02-21T10:05:00.002-05:00

Followup to my previous post, related to Kaveh's comment. This post describes how I set up HDMI TX and RX.
To test HDMI TX and RX, I loaded the HDMI switch example from Xilinx App Note 495. Loaded Top-level files dvi_demo.v and dvi_demo.ucf into ISE WebPACK, along with all the lower-level modules they require. Everything is in xapp495.zip from Xilinx.
Board configuration:
JP6&JP7 in: link SCL/SDA between TX&RX.
JP11 in: boot from USB stick.
JP5 in: Enable J1 HDMI input.
Connected J2 to display, J3 to source (J1 sometimes works as well).
I load dvi_demo.bit from a USB stick - takes about 30 seconds each time.
Tested with a Samsung TV and DirecTV box and Samsung BluRay.
The LED's show that RX is sync'ing with the signal and the display shows up on the TV. Tried several channels at different resolutions (no 1080p ones available). Sometimes had to unplug and replug the HDMI cables to get things to sync up. Just video, no audio passing through yet for some reason.
So that's my progress so far.

Atlys and HDMI on Linux

2011-01-12T19:28:00.004-05:00

Xilinx App Note 495 describes sample implementations of DVI/HDMI receiver and transmitter on the Digilent Atlys board. I built the code using WebPACK 12.4, and it works as advertised: The colorbar test pattern displays nicely on my HDMI monitor.

Also installed Digilent's Linux version of their Adept tools for FPGA programming. They don't seem to have the full GUI version available, but the command-line tool was able to load my test code (as a WebPACK-generated .bit file) into the Atlys FPGA with no problem. Don't see any way to load code into the SPI flash: it appears that Windows-based tools are still needed for that.

Only one minor glitch: I use Debian, which isn't one of Digilent's supported distributions. In recent versions of Debian, the udev package doesn't allow plugin devices to have protection mode 0666, which means that the Digilent tools will only work if run as root.
The fix is to edit "/etc/udev/rules.d/52-digilent-usb.rules" and add a group:
SYSFS{idVendor}=="1443", MODE="666" GROUP="plugdev"
then any user in the "plugdev" group can run the Digilent tools. The /etc/group file should have a line like
plugdev:x:46:jr
where "jr" is my username.

Digilent Atlys

2010-12-29T10:56:00.005-05:00

For Christmas, Santa Claus brought a Digilent Atlys development board for the Xilinx Spartan-6 FPGA's. Nice board, with a bunch of peripherals (Ethernet, USB, audio, HDMI!, etc).
The HDMI interface and protocol is implemented as firmware in the FPGA. My only test so far was to connect an HDMI output to a monitor and power up the board. It generates a test pattern of colored squares right out of the box. Nice. 2011 is going to be interesting.
While setting it up, I also noticed that Digilent now provides tools for Linux programming and communication with their FPGA boards. Need to check those out as well.

Saltwater immersion testing

2010-11-24T11:00:00.003-05:00

I've been working on a project that uses a custom A/D-FPGA board to generate and process sonar signals. Basic functionality is working, so the client took it to the dock for some live testing.
The testing included an "unscheduled" saltwater immersion experiment, with power applied to the board no less.
It was recovered after 24 hours; effects on the circuit were not beneficial.
So far, it looks as if the flash memory and A/D converters survived with just minor corrosion on the leads. The FPGA is interesting: definitely nonfunctional, and there's a pit where the epoxy case is crumbly. I suspect that the 1.2 volt switching regulator went out of range and fried the FPGA core.
Next time we plan to use a waterproof case.

Grub-ing

2009-11-06T22:27:00.002-05:00

Just got a nice Gateway quad-core PC to speed up FPGA designs, so time to install Debian Linux on it. Install went smoothly, until I tried to boot into Linux for the first time. Then I get error messages:
ata1: softreset failed (device not ready)
ata2: softreset failed (device not ready)
and Linux hangs.
After a lot of Google-ing and hacking (and hair-pulling), I finally found the problem: The Debian installer set the boot partition on the SATA drive to /dev/sdb3, and it really should have been /dev/sda3. Still get the "softreset failed" errors, but Linux boots and seems to operate normally.
Thinking about the problem: I used a USB DVD drive for the install, and then disconnected it before booting. I suspect the DVD was sda and the sata disk was sdb during the install, and the sata became sda when booting without the DVD drive.

915MHz signal with a 100MHz A/D

2009-08-10T15:46:00.003-04:00

I've been using a Radiotronix DP-1205 RF transceiver that operates in the 915MHz unlicensed ISM band. The power level, operating frequency, FM deviation, etc., are set using the SPI serial interface. So I decided to see if my MHZ100Q A/D PCB could see the signal. I bypassed the antialiasing filter and associated buffer, and then coupled the transceiver signal to the input.
It Works! The signal is low amplitude (less than 10% of full scale), and there are a lot of spurs 20dB down or so, but the carrier is clearly visible. The 902 to 928 MHz band is being undersampled at 100 MHZ so it shows up at 2 to 28 MHz in the digitized signal (in full compliance with Nyquist's rules).
The A/D is only spec'ed to 550 MHz, so I wouldn't trust the signal and distortion levels, but it's definitely a usable signal.
More details on the MHZ100Q project site at Source Forge.

MHZ100Q - on sourceforge

2009-04-15T15:25:00.004-04:00

I can now digitize one signal at 100MHz using my A/D card, capture in the Digilent Xilinx FPGA board, and upload to a PC via the USB port. I'm using Octave to upload and display the data, making a sort of oscilloscope. So I decided it's time to create a sourceforge open-source project.
It's http://mhz100q.sourceforge.net . Code is all in Subversion. It's all there, but I still need to create some build instructions and other documentation.

Cypress CY7C68013A (FX2) USB to FPGA

2009-03-02T10:36:00.004-05:00

I just got the USB interface working under Linux for the Digilent Nexys and Nexys 2 FPGA boards. Started with some ideas from the blog at braiden.org , updated the FX2 firmware and added from VHDL test code. Details at www.sensicomm.com/main/projects/fpga/ieee_fpga.shtml#nexys_usb .

Noise-blog

2009-02-14T11:35:00.003-05:00

Created a separate blog for less-technical happenings. (Signals here, random noise there). It's at noise-blog.sensicomm.com. Alternate is joerothweiler.blogspot.com (most noise-related names on blogspot are already taken).

Quad 100 MHz A/D PCB

2008-12-09T20:00:00.003-05:00

The paying customers are taken care of for a while, so it's time to update the blog. I want to test some DSP on the FPGA (filters, RF signal modulation/demodulation, etc)., so I need A/D and D/A capability. I could buy a board, but it's more fun to build my own. So I settled on a quad, 8-bit, 100MHz board that interfaces to the Xilinx or Digilent board via the 100-pin FX/2 connector. The block diagram shows one of the 4 channels. As a test, I'm capturing a signal and displaying it on the VGA output. The signal is looking reasonable. More details on my website:
http://www.sensicomm.com/main/projects/fpga/quad_100mhz_a2d.shtml

FPGA frequency counter code.

2008-07-21T16:56:00.003-04:00

An FPGA project that does something useful: implements a frequency counter using the Xilinx Spartan 3AN development board. Basically consists of two counters and the AX8 uC core. The first counter generates a 1 Hz timing signal from the on-board 50 MHz crystal oscillator, and the second counter counts the signal under test. The AX8 core runs a simple program that reads the count value and formats it for display on the LCD.
The attached image is counting the frequency of a VEX RC transmitter using a 75.97 MHz crystal. The measured count is 75.971459 MHz, which is within 0.002% of the expected value. The development board uses an xtal oscillator marked AGXO-751L 50.000 A. I found a datasheet at www.inysa.es indicating that A versions are 100ppm, or 0.01%, so the measured value is well inside the tolerances.
I'll be posting the code when I get it ready.

Dying Disk.

2008-07-14T10:05:00.003-04:00

My old Winbook laptop (100 MHz 486!) finally died. I was using it as a private webserver, mail collector, Christmas light controller, remote access when I'm away, etc. So it's been running 24/7 for about 5 years now. The battery died several years ago, and the hinge cracked, but the guts still worked fine and it doesn't suck too much power. So, if it ain't broke too bad, don't fix it.
Finally, the disk started sticking: I have to pick up the PC and shake it to get the drive to start spinning so it can boot. Now the fun part: I decided to move the drive to a new PC and copy all the settings off before it died completely. Unfortunately the disk was too big for the BIOS in the 486, so it's formatted with an OnTrack DiskManager partition hack, and the new PC (running a Debian Linux 2.6 kernel) doesn't see the real partitions. Google found 2 couple of suggestions: Add the hda=remap or hda=remap63 kernel option in grub (didn't help), or use device-mapper (didn't find any instructions on how to actually do it). Apparently, DM support was deleted in 2.6. So, I rebooted with a 2.4 kernel, whacked the drive with my hand, and all my partitions were readable without changing any settings.
The disk did die for good shortly after that. I suppose I could dig up an old 2.5 drive and get a few more years out of the 486, but I think I've gotten my money's worth.
I think I'll get the backups on my main PC up to date, then go back to useful work.

FPGA to VGA port

2008-06-17T13:26:00.003-04:00

I wrote a VHDL test module to display a set of color bars on the VGA port of the Spartan 3AN development kit. It's hard-coded for 640x480 and uses counters and gates to generate the bars, so it's mainly useful as a hardware sanity check. There's a link to the code on my main website, in case anybody wants to look at it.

AX8 core, UART, and uC programming

2008-05-23T10:16:00.003-04:00

Progress! I got the AX8 core (a uC based on the Atmel AVR instruction set, available from opencores.org) running on the Xilinx Spartan-3an eval board. It writes to the UART core, and I can see the UART's output on my PC.
Since it takes 7 minutes or more to recompile an FPGA design, I decided to set up data2mem. That's a Xilinx-supplied tool to update just the contents of internal RAM blocks without doing a full recompile. It took quite a bit of searching, but I figured out how to do it, and it works fast.
Details are online at
> www.sensicomm.com/main/projects/fpga/AX8_on_Xilinx.shtml

Page Counter for this blog

2008-05-22T09:56:00.002-04:00

I decided to add a page counter, to see if anybody's actually reading my blog. There are lots around, but I wanted something simple. I have a personal page with Verizon, so I decided to use one of their page counters. Turned out to be pretty easy:
First, I created file counter_blog.html on my Verizon-hosted page which is just:
<html><head></head><body>*** code to make a counter***</body></html>
Where the body is just an image tag. Details are from the service provider.
Now, to put it on this blog, I just used the "add html" option under "layout" on the dashboard, and added an iframe like this:
<iframe src="http://mysite.example.com/counter_blog.html" width=180 height=40></iframe>
And that's it. Happy reading.

fpga uC core

2008-05-03T11:31:00.003-04:00

For most things, I'll need a microcomputer core on the FPGA. Xilinx has the Microblaze and Picoblaze synthesizable cores, but I want something that's open-source. That way I can see how things are done and modify as desired.
There are several open cores available. I settled on the AX8 from opencores.org. It's fairly simple, but it implements most of the Atmel AVR instruction set (which I have a lot of experience with). A simple "Hello World" in this core turned out to be pretty straightforward.
After downloading AX8 from opencores, I loaded A90S1200.vhd, AX8.vhd, AX_TC8.vhd, and AX_Port.vhd into ISE WEBPACK. Then I modified A90S1200.vhd to divide the clock down to a lower frequency and to invert the reset line (since the core is set up for an active-low reset and most of the buttons on the board are active-high). I then created a .ucf file to attach port D to the LED's.
The test program just writes to port D to blink the LED's. I assemble the program with tavrasm, then convert the program to a rom vhdl file using the hex2rom program that's included with AX8.
And that's it!. Build in ISE, download to the FPGA, and the LED's blink.
I can post source if anybody's interested.

VHDL HelloWorld

2008-05-01T13:19:00.000-04:00

First step is to write a "Hello World" program. This one just counts cycles of the input clock, and displays a binary count on the LED's. Sample code is included here. hello.vhd implements the counter and connects to the LED's. The ucf file defines the clock and LED connections on the board.These would need to be changed to use anything other than this specific Spartan 3AN development board.
It loads and the lights blink, so now we can do some real work.


-- $Id: hello.vhd,v 1.1 2008/05/01 15:18:18 jrothwei Exp $
-- Joseph Rothweiler, Sensicomm LLC Started 16Apr2008.
-- "Hello world" program. Count down the clock, and display a binary
-- count on the 8 LED's.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;      -- Common things.
use IEEE.STD_LOGIC_ARITH.ALL;     -- Makes the "div+1" instruction work.
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
 Port (
   CLK_50M : in  STD_LOGIC;  -- Input: 50 MHz clock.
   LED : out  STD_LOGIC_VECTOR (7 downto 0)
 );
end main;

architecture Behavioral of main is
 signal div: STD_LOGIC_VECTOR(29 downto 0);
begin
 process(CLK_50M) begin
   if rising_edge(CLK_50M) then
     div <= div+1;              -- Increment counter on every clock.
     LED <= div(29 downto 22);  -- Display the counter MSB's on the LED's.
     end if;   end process; end Behavioral;


# $Id: hello_3an.ucf,v 1.1 2008/05/01 15:23:01 jrothwei Exp $
# Joseph Rothweiler Sensicomm LLC started 01may2008.
# Settings for the Xilinx Spartan-3AN development board by Digilent.
# This file just contains the parts I'm using.

#################################################
# Settings specific to this Board.
CONFIG VCCAUX = "3.3" ;
CONFIG ENABLE_SUSPEND = "FILTERED" ;
CONFIG POST_CRC = "DISABLE" ;

#################################################
# The main onboard clock, with the recommended settings.

NET "CLK_50M"       LOC = "E12"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN  10.000 VALID 20.000 BEFORE "CLK_50M" ;
OFFSET = OUT 20.000 AFTER "CLK_50M" ;

#################################################
# The row of 8 LED's above the switches.

NET "LED<0>"        LOC = "R20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<1>"        LOC = "T19"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<2>"        LOC = "U20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<3>"        LOC = "U19"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<4>"        LOC = "V19"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<5>"        LOC = "V20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<6>"        LOC = "Y22"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<7>"        LOC = "W21"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Starting FPGA project

2008-04-23T15:19:00.000-04:00

I've just started working with the Xilinx Spartan-3AN development board. First step was getting the USB interface to work with my Debian 32-bit Linux system. Fortunately, the latest (10.1) version of the Xilinx ISE WebPACK software supports a nice interface using the libusb package. Notes on the system are now on my website, at www.sensicomm.com/main/projects/fpga/ieee_fpga.shtml